The present invention relates to a method of fabricating complementary metal oxide semiconductor (CMOS) integrated circuits ICs), and more particularly to a method of fabricating CMOS ICs wherein increased performance is obtained in the support and logic device regions, without negatively impacting the array device region. Specifically, the present invention provides a method of fabricating a CMOS IC wherein the support gate is notched for high-performance without impacting the array device region. The prevent invention also provides CMOS ICs formed by the inventive method which include notched support gates and diffusion contacts that are borderless to the gate conductors.
The accelerating rate of improvement in the performance of advanced generations of CMOS ICs has been enabled by the aggressive scaling of the minimum lithographic feature size and supply voltages as well as innovations in the transistor structure, and the addition of higher-levels of systems functionality of the IC design. The combination of on-chip embedded memory such as eDRAM (embedded dynamic random access memory) with advanced CMOS logic is one means of increasing IC functionality and hence improving the performance of advanced generation of CMOS ICs.
Insofar as innovations in transistor structure are concerned, several key features have been incorporated into conventional transistors that are responsible for improving the performance of the same. These key features include:
(a) insertion of a Notched-Poly process;
(b) implant and anneal optimization;
(c) thin physical gate dielectrics (on the order of about 2 nm or less); and
(d) change from titanium silicide to cobalt silicide.
A detailed discussion concerning the above features and their importance in improving the performance of conventional transistors is found in T. Ghani, et al., xe2x80x9c100 nm Gate Length High Performance/Low Power CMOS Transistor Structurexe2x80x9d, 1999 IEDM Technical Digest, pp.415-418. Despite disclosing MOSFETs with notched gates that enable shorter than lithographic channel lengths, the T. Ghani, et al. article is applicable to a logic process (i.e., it contains no insulating cap) and does not accommodate for the formation of borderless contacts to diffusion regions.
In view of the drawbacks in the prior art, there is a need for developing a method for fabricating a MOSFET with a notched gate in an eDRAM process employing diffusion contacts that are borderless to the gate conductor.
One object of the present invention is to form transistors, i.e., MOSFETs, in support regions having channels that are shorter than that which can be formed utilizing conventional lithography, and at the same time, selectively maintaining longer channels for certain devices in array regions such as the memory array of a DRAM device.
Another object of the present invention is to provide a method wherein increased performance can be achieved in both the support and logic regions of a CMOS IC, without impacting the memory array transistor.
A further object of the present invention is to provide a method of fabricating a CMOS IC having short channels in the support regions and longer channels in the array regions that utilizes simple, yet CMOS compatible processing steps.
These and other objects and advantages are achieved in the present invention by employing a method which includes at least the steps of: forming a notch profile at the bottom of the gate of the CMOS logic transistor to shorten the channel length; and depositing and etching back a gapfill film over the wafer which will overfill the tight-pitch array region and underfill the relaxed-pitch support CMOS region, thereby delineating the array and support regions of the wafer.
Specifically, the method of the present invention includes the following processing steps:
(a) forming a gate stack on a surface of a substrate, said gate stack comprising at least a gate dielectric having a gate conductor formed thereon and said substrate includes array device regions and support device regions;
(b) protecting portions of said gate stack in said array and support device regions, while leaving other portions of said gate stack exposed;
(c) partially etching said exposed portions of said gate stack so as to remove some, but not all, of said gate conductor;
(d) forming a gapfill film on said protected gate stack and on said partially etched gate stack in said array and support device regions;
(e) removing said gapfill film from said support device regions, while selectively removing said gapfill film from said array device regions so as to leave gapfill film between adjacent protected gate stacks;
(f) forming spacers on any exposed sidewalls of said protected gate stacks in said array and support device regions;
(g) removing exposed gate conductor in said array and support device regions;
(h) providing an undercut in lower exposed regions of said gate conductor of said protected gate stacks in said array and support device regions; and
(i) removing remaining gapfill film from adjacent protected gate stacks in said array device region.
Following steps (a)-(i) above, conventional processing steps are used in completing the CMOS IC device which includes a notched gate in the support device region and contacts that are borderless to diffusion regions.
In addition to the above method, the present invention also relates to CMOS ICs that are formed therefrom. Specifically, the inventive CMOS ICs comprises:
a substrate having source and drain diffusion regions formed therein, and comprising array device regions and support device regions;
notched gates formed in said support device regions on portions of said substrate that do not include said source and drain diffusion regions; and
gates formed in said array device regions on portions of said substrate that do not include said source and drain diffusion regions, wherein some of said source and drain diffusion regions in said support and array device regions contain borderless diffusion contacts.